A semiconductor memory device represented by a DRAM (Dynamic Random Access Memory) includes a memory cell array having memory cells disposed at intersections between subword lines and bit lines. The semiconductor memory device may include hierarchically structured main word lines and subword lines. The main word line is a word line positioned at an upper hierarchy, and is selected by a first portion of a row address. The subword line is a word line positioned at a lower hierarchy, and is selected based on a corresponding main word line and a word driver line selected by a second portion of the row address.
A memory cell array included in a semiconductor memory device such as the DRAM may be divided into a plurality of memory mats to reduce the wiring capacity of the subword line and the bit line. The memory mat refers to an extending range of the subword line and the bit line. The main word line described above is assigned in plurals to one memory mat, so that when the main word line is selected using the first portion of the row address, the memory mat to be selected is also determined at the same time.
The driving process of the subword lines is carried out by subword drivers, and when the subword line is driven to an active potential, the memory cell is connected to the corresponding bit line. On the other hand, during a period in which the subword line is driven to a non-active potential, the memory cell and the bit line are kept in a cut-off state.
In driving subword lines to the active potential, relatively high voltages are provided to the subword drivers of a memory mat. In contrast, in driving the subword line to a non-active potential, relatively low voltages are provided to the subword drivers of the memory mat. The relatively low voltages that are provided while the subword lines are driven to the non-active potential establishes a condition for transistors of the subword drivers that may result in leakage currents. For example, the relatively low voltage provided to a source of a transistor of the subword driver while a relatively high voltage is provided to a gate of the transistor and a relatively low voltage is provided to the drain of the transistor may result in voltage differences sufficient to induce leakage currents in the transistor. An example of leakage currents may be gate induced drain leakage (GIDL).
Leakage currents increase power consumption by a semiconductor memory device. In systems where low power consumption is important, leakage currents may cause unacceptable power consumption. Therefore, reducing leakage currents in semiconductor memory devices may be desirable.